Electronics and Electrical Engineering The University of Edinburgh

Example PhD projects

The Silicon Technology Research is locating in the Scottish Microelectronics Centre (SMC) , a purpose built facility at the University's Science and Engineering campus at King's Buildings. The complex consists of approximately 250m2 of class 10 cleanrooms and 1000m2 of office and laboratory space. £3.2M of new equipment is in the process of being procured and detailed information is available concerning both the existing equipment and items which are in the process of being procured. The equipment available includes e-beam and 5 × and 10 × i-line and g-line wafer steppers, double sided aligners, a high current implanter, 12 furnace tubes (including LPCVD) and RTP systems as well as RIE etch (including deep etch), CMP equipment and metallisation systems. In addition there is extensive measurement capability which includes a Vickers Quaestor, Dektak profilometer, ellipsometry, an HP 4061 CV system and three HP4062 parametric test systems. MIAC (The Microelectronic Imaging and Analysis Centre), within the Department houses state-of-the-art SEMs, FIB (Focused Ion Beam) and AFM (Atomic Force Microscope) equipment. The above facilities have the capability to fabricate both sub-micron integrated circuits and Micro-Electro-Mechanical Systems ( MEMS ).

This core capability and the associated technologies that are available provide an excellent resource for research projects to draw upon. The group also has access to the complete range of Avant! process and device simulation software and the RS/1 suite of software for the Design of Experiments (DOE) and statistical analysis.

The group has very extensive expertise across a broad spectrum and has the capability to undertake research activities in most areas related to semiconductor technology and MEMS. The research group also has very strong connections with the semiconductor industry in both the UK and overseas and it is expected that most PhD projects will also foster these strong links. Background information about the Research Group is available from the STRG home page and links to some of the research activities the group is involved with are available below:

The above capability enables the Department to offer a very broad range of PhD projects related to microelectronic microfabrication and microsystems for which some of the broad topic areas are listed below.

The following list gives examples of possible PhD projects. It is not intended to be comprehensive and if you wish to pursue a research activity that is not listed below please contact Prof A.J. Walton (Anthony.Walton@ee.ed.ac.uk) - there is every possibility that we will be able to arrange a suitable project.

EPSRC studentship in Spatial Light Modulator Modelling and Characterisation.

This studentship forms part of the EPSRC funded ELITE (Enhancing the LInk between TEst and design of miniature liquid crystal displays) collaborative project. The project was funded by the Secretariat for Electronic Product Design and Manufacture of the EPSRC. The industrial collaborators are Micropix Technologies, GEC Marconi, Domain Solutions and Avant! (The former two are actively involved in microdisplays while the latter two are in the software modelling business.) The work of the ELITE project compliments that of the PACMAN project; a significant degree of interchange is expected between the project teams.

The overall aim of the project is to strengthen the link between characterisation/testing and design of silicon backplane microdisplays thereby reducing design time and improving the accuracy of the CAD process. This will be accomplished by developing a CAD based optoelectronic model of a microdisplay whose parameters are measured in the characterisation/test procedure. A theme is to use existing CAD tools as far as possible and to adapt them rather than to write custom code from scratch. The studentship will follow a parallel but more speculative path, looking at coherent applications of the devices

The successful candidate will have demonstrated, in their application, the ability to carry out both experimental and computer based research. The experimental work will involve designing, evaluating and optimising coherent optical characterisation techniques for liquid crystal spatial light modulators. Model development, evaluation and optimisation will be carried out by computer using, as far as possible, existing simulation tools such as HSPICE or Avant!'s Liquid. We are particularly interested in the degree of phase noise which is (a) likely to arise from device imperfections, and which can (b) be tolerated in specific applications.

The student will be be supervised by Dr I. Underwood (Ian.Underwood@ee.ed.ac.uk), with co-supervision by other members of staff as

Micro Electro Mechanical Systems (MEMS)/ Micro-Systems Technology (MST)

There are a large number of opportunities to work interdisciplinary projects which involve the fabrication of sensors and actuators. These include the Royal Observatory (bolometers), Opthalmology (drug delivery systems), Mechanical engineering (miniature hydraulic systems), Pharmaceutical Science (micro dialysis), Bio-Engineering (medical implants), Physics (micro-deformable mirrors). There are also some exciting opportunities associated with the design and fabrication of bio-chips.

For more information contact Prof A.J. Walton (Anthony.Walton@ee.ed.ac.uk)

Fabrication of Nanostructures

The Department has developed an ultrahigh resolution electron beam lithography tool for fabrication of electronic structures at dimensions in the range 10-50nm. This unique tool is installed in an industrial grade cleanroom facility and it is characterised down to 70nm dimensions for MOS transistor fabrication and down to 30nm linewidths for simple patterns. The objective of the new project is to explore the possibilities for patterning structures at dimensions down to 10nm linewidth and then to apply the learned techniques to the fabrication of novel electronic and/or mechanical structures at these extremely small dimensions. The project presents an exciting opportunity to access a world-class nanolithography tool and to contribute to a stimulating field of international research.

For more information contact Dr R. Cheung (Rebecca.Cheung@ee.ed.ac.uk)

New Techniques for Physical Analysis of Microelectronic Devices

Leading R&D laboratories world-wide are already developing miniaturised silicon technologies at dimensions down to the 100nm level. These new technologies will provide the 2GHz pentium processors and 4Gbit DRAM chips of the future. While it is difficult for university based research to compete head-on with this type of industrial R&D work, there is considerable opportunity to develop new methodologies for analysing the physical construction of these new devices. This provides a strong basis for industrial collaboration, at the same time offering considerable opportunity for research innovation. The proposed project will initially explore novel use of existing techniques such as focused ion beam, atomic force microscopy and energy dispersive x-ray spectroscopy in order to provide increased resolution and hence more accurate analysis of the physical structure of sub-100nm transistors. Considerable interaction with leading microelectronics R&D sites is anticipated and will be strongly encouraged.

For more information contact Dr R. Cheung (Rebecca.Cheung@ee.ed.ac.uk)

Investigation of 3-D Mapping of the Physical Structure of Microelectronic Devices

The requirement for industry to construct microelectronic devices which are essentially 'identical' at each and every site across a 200mm diameter silicon wafer - typically as many as a one billion devices - presents a very considerable manufacturing challenge. When a circuit fails due to a single faulty device it is usually important to locate the device and then identify the cause of the failure. In state of the art devices this could be the result of just a few atoms being in the wrong place! The aim of this project is to explore whether atomic resolution or near atomic resolution mapping of devices can be carried out in 3-dimensions to detect these 'mis-placed' atoms. This is a very challenging area of research which offers considerable opportunity to study microengineered structures and devices at the resolution limits of modern microscopy. The project should, if successful, lead to the development of a novel microscopy or analysis tool.

For more information contact Dr R. Cheung (Rebecca.Cheung@ee.ed.ac.uk)

Optimisation of the Integrated Circuit Manufacturing Process

The manufacturing process results in a spread of device characteristics which must be charaterised. From a practical viewpoint this provides manufacturers with a dilemma because the accurate extraction of the most important electrical characteristics (SPICE parameters0 is a time consuming business. Work in this area involves the use of Technology CAD (TCAD) to characterise processes and the development of techniques to both model and predict varaitions both at the device and circuit level.

For more information contact Prof A.J. Walton (Anthony.Walton@ee.ed.ac.uk)

Microelectronic Test Structures

The department has a long record in the design, fabrication, measurement and analysis fo microelectronic test structures that are used to characterise the Integrated Circuit (IC) fabrication process. More information on this general activity is available about research on microelectronic test structure taking place within in the Department. There are many potential projects in this area which includes a project on interconnect characterisation in collaboration with NIST

For further details contact Prof A.J. Walton (Tel: 0131 650 5620, Email: Anthony.Walton@ee.ed.ac.uk).

Optimisation of Test Structure Performance Using a Statistical Approach

Test structures are widely used to monitor the performance of the manufacturing lines producing integrated circuits. However, the layout and measurement of these devices has not been rigorously optimised for maximum sensitivity or robustness. This project would use simulators which have recently become available to model both existing and new structures to theoretically optimise their performance. These results would then be used together with statistically designed experiments to verify the theoretical approach and provide formal design rules for test chip engineers. The project will make extensive use of state-of-the-art TMA process and device simulators and the BBN RS series of software for experimental design and analysis.

For more information contact Prof A.J. Walton (Anthony.Walton@ee.ed.ac.uk)

Optical Structures by Silicon Micromachining

Keywords: silicon micromachining. Many optical elements can be realised using techniques very similar to those used for conventional silicon processing. This project will involve the investigation, construction and characterisation of such optical elements.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk) or Dr A.M. Gundlach (amg@ee.ed.ac.uk)

Fabrication of Miniature Liquid Crystal Displays

Keywords: liquid crystal display. The STR Group in EE and Applied Optics Group in Physics have developed a technology for sub-miniature liquid crystal displays (LCDs). A current PhD project is looking at the implementation of colour and 3D. (email iu@ee.ed.ac.uk or talk locally to Iain Rankin for details or a demo.) This project will look at optimising the design and fabrication of the LCD module for enhanced performance eg higher contrast, fewer defects, more grey levels / colours etc.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk) or Dr D Vass (Dept Physics)

Applications of Miniature Liquid Crystal Displays

Keywords: liquid crystal display. The STR Group in EE and Applied Optics Group in Physics have developed a technology for sub- miniature liquid crystal displays (LCDs). A current PhD project is looking at the implementation of colour and 3D. (email iu@ee.ed.ac.uk or talk locally to Iain Rankin for details or a demo.) This project will look at optimising the display system (LCD module plus other components) for one or more applications, eg, head mounting, video, VR, projection etc.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk) or Dr D Vass (Dept Physics)

Addressing Miniature Liquid Crystal Displays

Keywords: liquid crystal display. The STR Group in EE and Applied Optics Group in Physics have developed a technology for sub-miniature liquid crystal displays (LCDs). A current PhD project is looking at the implementation of colour and 3D. (email iu@ee.ed.ac.uk or talk locally to Iain Rankin for details or a demo.) This project will look at the transfer of data in various forms (eg analogue / digital, encoded / unencoded) to the LCD and the practical implementation of appropriate interface circuitry.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk)

Spatial Light Modulators with non Cartesian Pixel Arrays

Keywords: spatial light modulator, optical interconnect. To date optical and optoelectronic computing and interconnect systems have concentrated on transforming arrays of points on a square grid. Many systems could operate more efficiently using other pixel grids eg hexagonal or ring / wedge. This project will investigate both theoretically and experimentally, using small test devices, the use of such pixel grids.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk)

VLSI design for Liquid Crystal Spatial Light Modulators

In a wide ranging collaboration involving the STRG, EU Physics Department and a number of industrial collaborators we have developed an optoelectronic device technology for Spatial Light Modulators (SLMs) involving liquid crystal over silicon backplanes. Further opportunities are available to design silicon backplanes for liquid crystal SLMs.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk) or Dr D Vass (Dept Physics)

VLSI Design for Smart Pixels

Keywords: spatial light modulator, smart pixel. Smart Pixels are small islands on a silicon chip accesses via optical input and output to overcome the conventional electronic pinout bottleneck. Opportunities exist to carry out VLSI design of smart test pixels and smart pixel arrays in either of two technologies - liquid crystal over silicon or SEED over silicon flip-chip.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk) or Dr D Vass (Dept Physics)

Optoelectronic Neural Networks incorporating Spatial Light Modulators

Keywords: neural network, optoelectronic, spatial light modulator. In a wide ranging collaboration involving the ISG, STRG, EU Physics Department and a number of industrial collaborators we have developed an optoelectronic device technology for Spatial Light Modulators (SLMs) involving liquid crystal over silicon backplane. The technology has potential for the optoelectronic implementation of some neural network architectures. The project will involve the design, implementation and characterisation of one or more neural systems using currently available SLMs.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk) or Prof A.F. Murray (afm@ee.ed.ac.uk)

Optoelectronic Neural Network Architectures

Keywords: neural network, optoelectronic. This project will involve a mainly theoretical (but also backed up by experimentation) analysis of the potential of optoelectronics for the implementation of neural networks. The emphasis will be on the use of realistic performance parameters (rather than wish lists or blue sky estimates) for the device technologies concerned.

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk) or Prof A.F. Murray (afm@ee.ed.ac.uk)

Optoelectronic Implementation of Radial Basis Functions

Keywords: radial basis function, optoelectronic, spatial light modulator. This project will involve a study of Radial Basis Functions (RBFs) for implementation optoelectronically. The emphasis will be on the design of systems which are compatible with currently available devices and components

For more information contact Dr I. Underwood (iu@ee.ed.ac.uk) or Dr S. Maclaughlin (sml@ee.ed.ac.uk) Ian Underwood / Steven Maclaughlin

Gate dielectrics for advanced devices.

Keywords: gate dielectric, deep submicron devices, interface

As device dimensions are scaled to accommodate gate lengths below 0.5 micron the properties of the gate dielectric itself becomes increasingly difficult to control and predict. This dielectric has been identified as one of the key research areas for advanced submicron devices. It is necessary to form the gate dielectric at thicknesses less than 100 nm with a uniformity of better than 2% on wafer and wafer to wafer. The nature of the silicon/dielectric interface must be well understood and controlled and the effect on the electrical performance must be determined and controlled. Key electrical parameters are the breakdown strength, oxide and interface trapped charges, wearout due to tunnelling and the effect of its use as an implant mask. There are stringent requirements where the dielectric will be used in EEPROM devices.

The aim of this project is to investigate the performance of some dielectric materials and formation methods for gate dielectrics in silicon ICs. Electrical test structures will be fabricated to assess dielectric performance including small geometry MOS transistors.

For more information contact Dr L.H. Haworth (lih@ee.ed.ac.uk)

Automated Layout Modification to Increase IC Yield.

Software to accurately estimate the manufacturability of IC has been developed within the department (EYES). This software also has the potential to be used to modify commercial IC layout to make it more robust to defects.

The project will use the EYE interpreter to develop algorithms to increase the robustness of IC layout to circuit shorts and breaks and also to introduce extra contacts. The algorithms developed will be applied to commercial IC layout to determine have useful they will be in practice and what yield improvement might be gained.

For more information contact Dr G.A. Allan (gaa@ee.ed.ac.uk)

Wafer Level Reliability Measurements

Wafer Level Reliability (WLR) has received increasing interest in recent years. This has been a result of the requirement to built in reliability rather that using testing to remove potentially faulty devices. This has been largely achieved by using DFM techniques and SPC but this does not totally prevent rogue batches with lower reliability levels getting through to the end of the process. The purpose of WLR is to detect these wafer and ensure that potentially unreliable devices do not get delivered to the customer. This requires that measurements must be both fast, so potentially every wafer can be tested, and also ensure that the measurement does not damage the adjacent product devices. Hence, a feature of WLR devices is a source of local heat and a method of monitoring the temperature [1-3].

Examples of the types of fast WLR tests include hot carrier measurements, passivation and interconnect dielectrics, gate oxide integrity [4], in-process charging [5], mobile ions [6], SWEAT (Standard Wafer-level Electromigration Test) [7], stress migration, via voiding, current crowding and junction spiking. Accelerated tests are best suited to monitor the rate of degradation of the materials used to build the IC. With mature processes it may then be possible to correlate these measurements with lifetime predictions. It should however be remembered that if this link is to be achieved then it must be ensured that the tests are not accelerated to such a degree that the WLR structure fails from a different mechanism than that which would normally cause a failure. This is especially the case for SWEAT tests if the wafer temperature or current levels are too high [1].

WLR structures must obviously be well characterised and may be located in the scribe channel or in a test chip when used to monitor production devices. The normal procedure is to first qualify the process using traditional lifetime tests. Then WRL fast tests can be used to provide a so called statistical signature of the process reliability. If the WLR measurements on product wafers show a similar distribution to those observed on the qualification lots then it can be assumed that the reliability of the devices on the wafer will be statistically similar to those observed during the qualification tests. However, if this is not the case then some other failure mechanism is probably present and the only way of ensuring reliability is to re-test using traditional reliability measurements. As reliability levels are pushed below 10 FITs it is expected that the use of WLR testing will become more important in ensuring the quality of devices reaching customers is of the desired level.

This project will be concentrating on researching methods of using WLR techniques to monitor the quality of thin oxides. It will involve the design, fabrication and measurement of WLR test structures. The measurements and device fabrication will be performed both in the Department and at Motorola with the measurements being undertaken on the latest generation of automatic parametric testers.


  1. J.A. Shideler, T. Turner, J. Reedholm, and C. Messick, "A systematic approach to wafer level reliability", Solid State Technology , vol. 38, no. 3, pp. 47-54, March 1995.
  2. T.E. Turner, "Wafer level reliability - Process-control for reliability", Microelectronics and Reliability , vol. 36, no. 11-12, pp. 1839-1846, 1996.
  3. A. Papp, F. Bieringer, D. Koch, H. Kammer, H. Pohle, A. Schlemm, M. Schneegans, and H. Vogt, "Use of Test Structures for a Wafer - Level - Reliability Monitoring", Proceedings of the 1996 IEEE International Conference on Microelectronic Test Structures , vol. 9, pp. 267-271, Trento, Italy, March 25-28, 1996.
  4. P. O'Sullivan and A. Mathewson, "Implications of a localized defect model for wafer level reliability measurements of thin dielectrics", Microelectronics and Reliability , vol. 33, no. 11-12, pp. 1679-1685, 1993.
  5. A.M. McCarthy and W. Lukaszek, "A New Wafer Surface Charge Monitor (CHARM)", Proceedings of the IEEE 1989 International Conference on Microelectronic Test Structures , vol. 2, no. 1, pp. 153-155, Edinburgh, Scotland, 13-14th March, 1989.
  6. R. Dreizner, J. Nagel, and R. Scharfe, "A new wafer level reliability method for evaluation of ionic induced pMOSFET drift effects", Microelectronics and Reliability, vol. 36, no. 11-12, pp. 1855-1858, 1996.
  7. "A Procedure for Executing SWEAT", JEP119, Electronic Industries Association, Sept 1994

For more information contact Prof A.J. Walton (Anthony.Walton@ee.ed.ac.uk)

Silicon Carbide Devices for Power Electronics

Silicon Carbide (SiC) - a wide band-gap semiconductor, is extremely useful for applications in high power and high temperature electronics, due to its high electrical breakdown field. However, a number of processing techniques still need to be developed and optimised before complex device and circuit applications can be realised. Moreover, questions such as: a) limit to device stability at high temperatures, b) effect of device response time as SiC devices shrink to the nanometre scale, are still to be answered. This project will involve device design, fabrication and process development with a view to optimise nano-devices in SiC for high temperature, high frequency operations.

For more information contact Dr R. Cheung (Rebecca.Cheung@ee.ed.ac.uk)

Silicon Carbide MEMS for Harsh Environments

Silicon Carbide is a promising material candidate for the development of microelectromechanical (MEM) systems. Because of its excellent electrical, mechanical and chemical properties, it is suitable for applications in harsh environments. The aim of this project will be to design experimental structures and develop the challenging processing techniques that are necessary for the realisation of prototype sensors and actuators.

For more information contact Dr R. Cheung (Rebecca.Cheung@ee.ed.ac.uk)

Photonic Crystals

The ability to control optical properties of materials has tremendous impact on a wide range of areas such as optical communications, high-speed computers and spectroscopy. The emerging area of creating artificial photonic crystals presents many challenges in both experimental and theoretical research. This project involves the development of both the theoretical framework and the fabrication techniques for the creation of photonic crystals. It is envisaged that such crystals could be engineered to prohibit the propagation of light, or allow it only in certain frequencies or localise light in specified areas.

For more information contact Dr R. Cheung (Rebecca.Cheung@ee.ed.ac.uk)

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